The present invention relates to an entirely integrated CMOS high voltage generator particularly suited for EEPROM memory devices and more in particular the invention concerns a voltage-boosted phase oscillator for driving a voltage mulplier circuit.
In integrated circuit (IC) where a voltage greater than the supply voltage of the device is needed, as in EEPROM memory devices, a peculiar circuit called voltage multiplier or voltage booster is used, which permits to obtain a voltage in the order of several decades of volts and is capable of delivering a current in the order of several decades of microampers (.mu.A) starting from a supply voltage of e.g. 5V.
This type of circuit is amply described in literature and is commonly associated with an oscillator which produces two phase signals, opposite in phase to one another, which are needed for driving the electrical charge transfer through the various stages of the voltage multiplier, in an unique direction from a supply terminal to an output storage capacitor, across which the multiplied voltage is produced. Each stage of the multiplier is basically constituted by a transfer diode and by a storage capacitor. The oscillation of the driving oscillator may be controlled by an output voltage regulating network in order to keep the output voltage constant independently of the load and/or of variations of the supply voltage. Commonly a ring oscillator is used which is implemented by simply connecting in cascade an odd number of inverters and by closing in a ring the chain of inverters, thus preventing the occurrence of a stable state of the ring. The instability is further ensured by the large gain of the CMOS gates which are normally used as inverters.
On the other hand, the basic circuit of the voltage multiplier has lately undergone several developments which have markedly increased its efficiency.
A recently developed voltage multiplying circuit is shown in FIG. 1. The voltage multiplier utilizes single type, n-channel transistors, preferably of the so-called natural or depletion type which advantageously offer a threshold voltage to 0V and an internal resistance under conduction which is decisively lower than that of the so-called enhancement type transistors. The circuit, which is conceptually similar to the basic circuit made with diodes, requires for its functioning two pairs of phase signals, namely: FBX and FBN (voltage-boosted phases) and FX and FN (normal voltage level phases). The phases of the two pairs are out of phase by 180.degree. . The normal level phases commonly have an amplitude equal to the supply voltage VCC, while the voltage-boosted phases have an amplitude larger than VCC.
Basically the limiting factor to ideality of operation of a voltage multiplier is represented by the inevitable presence of a threshold voltage of the transistors, which does not permit an ideal transfer of the charge from each stage to the successive stage and this becomes seriously penalizing when trying to obtain relatively high output voltage starting from a supply voltage (VCC) which is comparable, as order of magnitude, to the threshold voltage. Moreover the threshold voltage of MOS transistors suffers from the so-called "body effect" and the greater becomes the voltage, the greater becomes the threshold voltage, which tends to become equal to the amplitude of the phase signals provided by the driving oscillator. Therefore by increasing the number of the stages of the multiplier, a saturation condition is eventually reached which determines the maximum output voltage which can be practically obtained. The availability of a pair of voltage-boosted phase signals permits to obviate this phenomenon by increasing the gate voltage of the transistors which transfer the charges from each stage to the successive stage, e.g. of the transistor N2 of FIG. 1. The large capacitors C1 and C2 which provide the electric charges to the system for boosting the voltage on the output node OUT are connected to the normal, "not-boosted", phases FX and FN generated by the driving oscillator, while to the voltage-boosted phases FBX and FBN are connected smaller capacitors CB1 and CB2 because the circuit nodes driven by these transistors do not draw current, in fact they are connected to the gates of the transistors N2 and N1, respectively, which represent nodes having a substantially infinite impedance. In general, because the amplitude of the voltage-boosted phases, FBX and FBN, is markedly greater than the amplitude of the normal phases, FX and FN, also the nodes of the multiplier circuit driven by the voltage-boosted phases will be at a comparably higher voltage than the corresponding nodes driven by the normal phases FX and FN. By supposing that at a certain instant, the phases FX and FBX be rising in voltage, while the complementary phases FN and FBN be dropping in voltage, the nodes 1 and 3 will be coupled respectively by the capacitors C1 and CB1 and therefore will rise in voltage, on the contrary the voltage of nodes 2 and 4 will drop. At this stage the nodes 1 and 3 are not coupled among each other because the transistor N1 is off because the voltage of the node 4 is lower than the voltage of the node 3, being the node 4 driven by a dropping phase, and effectively the node 3 "sees" the infinite impedance of the gate of the transistor N2. The node 3 may thus reach a voltage higher than the node 1 and the transfer of charges from the node 1 to the node 2 may take place substantially without the loss of a threshold voltage until the voltage of the node 3 becomes greater than the voltage of the node 1 by at least the threshold voltage of the transistor N2 with the relative "body effect". On the contrary when, after half a period of oscillation, the node 1 drops and node 2 rises, similarly the node 3 drops and the node 4 rises, and therefore the decoupling transistor N1 switches-on and the transfer transistor N2 assumes a diode configuration, thus preventing the charges transferred during the preceding step from flowing back.
In a voltage multiplier of this type, any two complementary phase signals must essentially be always non-overlapped, i.e. they must never be simultaneously "high", because if such a condition would happen, a decrease of efficiency of the charge transfer process toward the output of the voltage multiplier, due to a back-flow of electrical charges caused by the simultaneous conduction of two adjacent stages of the circuit, would be observed.